This invention relates to a frequency synthesizer usable in various electronic apparatuses such as a transceiver.
Frequency synthesizers including a phase-locked loop (PLL) circuit are widely used in multi-channel transceivers. Conventional frequency synthesizers tend to consume electric power at high rates.
Japanese published unexamined patent application No. 62-16617 discloses an advanced frequency synthesizer in which a PLL circuit is intermittently activated and deactivated to save electric power. This prior-art synthesizer includes special components which serve to quickly stabilize the synthesizer output upon the activation of the PLL circuit.